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1 block diagram features ? ? f max < 2.5ghz ? ? 4 pairs of diferential lvds outputs ? ? low additive jitter, < 0.05ps (max) ? ? input clk accepts: lvds, lvds, cml, sstl input level ? ? output to output skew: <20ps ? ? operating temperature: -40 o c to 85 o c ? ? power supply: 3.3v 10% or 2.5v 5% ? ? packaging (pb-free & green) ? ? 16-pin tqfn available description te PI6C5922504 is a high-performance low-skew 1-to-4 lvds fanout bufer. te clk inputs accept lvpecl, lvds, cml and sstl signals. PI6C5922504 is ideal for clock distribution applica - tions such as providing fanout for low noise pericom oscillators. pin confguration ref_in+ vth ref_in- q0+ q0- q1+ q1- q2+ q2- q3+ q3- d le q en q1+ q1- q2+ q2- 1 2 3 4 12 11 10 9 16 15 14 13 5 6 7 8 ref_in+ v th v ref-ac ref_in- q3+ q3- v dd en q0- q0+ v dd gnd 2.5 ghz 1:4 lvds fanout bufer with internal termination PI6C5922504 PI6C5922504 rev a 08/14/2014 14-0127
2 pin description (1) pin # name ty pe description 1, 2 q1+, q1- output diferential output pair, lvds interface level. 3, 4 q2+, q2- output diferential output pair, lvds interface level. 5, 6 q3+, q3- output diferential output pair, lvds interface level. 7 v dd power core power supply 8 en input synchronous output enable, with internal 25k-ohm pull-up resistor. logic high selects enable, and logic low selects disable. 9 ref_in- input diferential in negative input, ac and dc coupled 10 vref-ac output reference voltage: biased to v dd -1.4v. used when ac coupling inputs 11 vth output diferential pair in center-tap node. tie to vref-ac for ac coupled inputs. 12 ref_in+ input diferential in positive input, ac and dc coupled 13 gnd power ground 14 v dd power core power supply 15, 16 q0+, q0- output diferential output pair, lvds interface level. functional description ref_in+ ref_in- en q+ q- 0 1 1 0 1 1 0 1 1 0 x x 0 0 1 PI6C5922504 rev a 08/14/2014 PI6C5922504 2.5 ghz 1:4 lvds fanout bufer with internal termination 14-0127
3 dc characteristics symbol parameter conditions min ty p max units v dd power supply voltage 3.0 3.6 v 2.375 2.625 v t a ambient temperature -40 85 o c i dd power supply current @3.3v 10%, loaded 88 105 ma @2.5v 5% loaded 58 75 r diff_in diferential input resistance (in+ to in-) 90 100 110 v ih input high voltage 1.2 v dd - 0.9 v v il input low voltage 0.4 v ih -0.1 v v in input voltage swing 0.1 v dd v v diff_in diferential input swing 0.2 v v ref-ac output reference voltage v dd -1.5 v dd -1.3 v dd -1.15 v lvcmos/lvttl dc characteristics (ta = -40 o c to +85 o c, v dd = 2.5v 5% to 3.3v 10%) symbol parameter conditions min ty p max units v ih input high voltage 2.0 v dd v v il input low voltage 0 0.8 i ih input high current -125 20 a i il input low current -300 a maximum ratings (over operating free-air temperature range) note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. tis is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may afect reliability. storage temperature .............................................. -65oc to+155oc ambient temperature with power applied ......... -40oc to+85oc 3.3v core supply voltage ......................................... -0.5 to +4.6v esd protection (hbm) ......................................................... 2000v PI6C5922504 rev a 08/14/2014 PI6C5922504 2.5 ghz 1:4 lvds fanout bufer with internal termination 14-0127
4 ac characteristics (t a = -40 o c to +85 o c, v dd = 3.3v 10%, 2.5v 5%) symbol parameter conditions min ty p max units f max output frequency 2.5 ghz t pd propagation delay v in < 40 0mv 370 470 570 ps v in 40 0mv 300 410 500 t sk output-to-output skew (2) 20 ps device to device skew 200 ps t s setup time 150 ps t h hold time 150 ps t r /t f output rise/fall time 20% - 80% 55 200 ps t odc output duty cycle f 1 ghz 48 52 % 1 ghz f < 2.5 ghz 40 60 % v pp output swing lvds outputs 250 800 mv t j bufer additive jitter rms 156.25mhz with 12khz to 20mhz integration range (3) 30 fs notes: 1. measured from the diferential input to the diferential output crossing point 2. defned as skew between outputs at the same supply voltage and with equal loads. measured at the output diferential crossing point 3. input source phase noise similar to phase noise plot in page 5 lvds dc characteristics ( t a = -40 o c to +85 o c, v dd = 3.3v 10%, 2.5v 5% ) symbol parameter conditions min ty p max units v out output voltage swing 250 325 400 mv v diff_ out diferential output voltage swing 500 650 800 mv v ocm output common mode voltage 1.15 1.35 v delta v ocm change in common mode voltage -100 100 mv thermal information symbol description condition ja junction-to-ambient thermal resistance still air 57.7 c/w jc junction-to-case thermal resistance 32.2 c/w PI6C5922504 rev a 08/14/2014 PI6C5922504 2.5 ghz 1:4 lvds fanout bufer with internal termination 14-0127
5 phase noise plots confguration test load board termination for lvds outputs 100 z = 50 o z = 50 o lv ds buffer v cc l = 0 ~ 10 in. PI6C5922504 rev a 08/14/2014 PI6C5922504 2.5 ghz 1:4 lvds fanout bufer with internal termination 14-0127
6 output swing vs frequency propagation delay vs temperature PI6C5922504 rev a 08/14/2014 PI6C5922504 2.5 ghz 1:4 lvds fanout bufer with internal termination 14-0127
7 application information suggest for unused inputs and outputs lvcmos input control pins it is suggested to add pull-up=4.7k and pull-down=1k for lvc - mos pins even though they have internal pull-up/down but with much higher value (>=50k) for higher design reliability. ref_in=/ ref_in- input pins tey can be lef foating if unused. for added reliability, connect 1k to gnd. outputs all unused outputs are suggested to be lef open and not con - nected to any trace. tis can lower the ic power supply power. power decoupling & routing vdd pin decoupling as general design rule, each vdd pin must have a 0.1uf decou - pling capacitor. for better decoupling, 1uf can be used. locat - ing the decoupling capacitor on the component side has better decoupling flter result as shown in fig. 1. fig 1: placement of decoupling caps diferential clock trace routing always route diferential signals symmetrically, make sure there is enough keep-out space to the adjacent trace (>20mil.). in 156.25mhz xo drives ic example, it is better routing diferen - tial trace on component side as the following fig. 2. clock timing is the most important component in pcb design, so its trace routing must be planned and routed as a frst priority in manual routing. some good practices are to use minimum vias (to- tal trace vias count <4), use independent layers with good reference plane and keep other signal traces away from clock traces (>20mil.) etc. fig 2: ic routing for xo drive clock ic device vdd 11 13 10 9 8 12 14 0.1uf 0.1uf gnd gnd vdd vdd decouple cap. on comp. side gnd clock ic device 2 ref_in - ref_in+ 3 4 5 6 vdd gnd keep out board vias vdd gnd 150 150 156.25m xo 0.1uf *100 *100 is optional if ic has gnd PI6C5922504 rev a 08/14/2014 PI6C5922504 2.5 ghz 1:4 lvds fanout bufer with internal termination 14-0127
8 lvpecl and lvds input interface lvpecl and lvds dc input lvpecl and lvds clock input to this ic is connected as shown in the fig. 3. lvpecl and lvds ac input lvpecl and lvds ac drive to this clock ic requires the use of the vref-ac output to recover the dc bias for the ic input as shown in fig. 4 cml ac-coupled input cml ac-coupled drive requires a connection to vref-ac as shown in fig. 5. te cml dc drive is not recommended as diferent vendors have diferent cml dc voltage level. cml is mostly used in ac coupled drive confguration for data and clock signals. fig 3: lvpecl/ lvds input fig 4: lvpecl/ lvds ac coupled input fig 5: cml ac-coupled input interface device ic + - zo =100 *150 *150 lvpecl drive ref_in+ ref_in - vth vref - ac 50 50 *150 removed for lvds device ic + - zo =100 ref_in+ ref_in - vth vref - ac 50 50 vdd 0.01uf 0.01u 0.01u lvpecl drive *150 *150 *150 removed for lvds device ic + - zo =100 cml ref_in+ ref_in - vth vref - ac 50 50 cml ac - coupled vdd 0.01uf 0.01u 0.01u hcsl ac-coupled input it is suggested to use ac coupling to bufer pcie hcsl 100mhz clock since its v_cm is relatively low at about 0.4v, as shown in fig. 6. cmos clock dc drive input lvcmos clock has voltage voh levels such as 3.3v, 2.5v, 1.8v. cmos drive requires a vcm design at the input: vcm= ? (cmos v) as shown in fig. 7. rs =22 ~33ohm typically. fig 6: hcsl ac-coupled input interface fig 7: cmos dc input vcm design device ic + - zo =100 ref_in+ ref_in - vth vref - ac 50 50 vdd 0.01uf 0.01u 0.01u 33 33 hcsl pcie ref_clk 50 50 cmos driver 3.3v, 2.5v, 1.8v rs zo ro ref_in+ ref_in - vdd 3.3v 0.1u rup rdn vcm design vcm cmos v rup rdn vcm 3.3v 1k 1k 1.65v 2.5v 1k 610 1.25v 1.8v 1k 380 0.9v diff. input vth vref - ac PI6C5922504 rev a 08/14/2014 PI6C5922504 2.5 ghz 1:4 lvds fanout bufer with internal termination 14-0127
9 device lvpecl output terminations lvpecl output popular termination te most popular lvpecl termination is 150ohm pull-down bias and 100ohm across at rx side. please consult asic data - sheet if it already has 100ohm or equivalent internal termina - tion. if so, do not connect external 100ohm across as shown in fig. 8. tis popular terminations advantage is that it does not allow any bias through from v dd . tis prevents v dd system noise coupling onto clock trace. lvpecl output tevenin termination fig. 9 shows lvpecl output tevenin termination which is used for shorter trace drive (<5in.), but it takes v dd bias current and v dd noise can get onto clock trace. it also requires more component count. so it is seldom used today. fig. 8 lvpecl output popular termination fig. 9 lvpecl tevenin output termination lvpecl output ac tevenin termination lvpecl ac tevenin terminations require a 150ohm pull- down before the ac coupling capacitor at the source as shown in fig. 10. note that pull-up/down resistor value is swapped compared to fig. 9. tis circuit is good for short trace (<5in.) application only. lvpecl output drive hcsl input using the lvpecl output to drive a hcsl input can be done using a typical lvpecl ac tenvenin termination scheme. use pull-up/down 450/60ohm to generate vcm=0.4v for the hcsl input clock. tis termination is equivalent to 50ohm load as shown in fig. 11. fig. 11 lvpecl output drive hcsl termination fig. 10 lvpecl output ac tenvenin termination PI6C5922504 rev a 08/14/2014 PI6C5922504 2.5 ghz 1:4 lvds fanout bufer with internal termination 14-0127
10 lvpecl output v_swing adjustment it is suggested to add another cross 100ohm at tx side to tune the lvpecl output v_swing without changing the optimal 150ohm pull-down bias in fig. 12. tis form of double termina - tion can reduce the v_swing in ? of the original at the rx side. by fne tuning the 100ohm resistor at the tx side with larger values like 150 to 200ohm, one can increase the v_swing by > 1/2 ratio. fig. 12 lvpecl output v_swing adjustment clock jitter defnitions total jitter= rj + dj random jitter (rj) is unpredictable and unbounded timing noise that can ft in a gaussian math distribution in rms. rj test val - ues are directly related with how long or how many test samples are available. deterministic jitter (dj) is timing jitter that is pre - dictable and periodic in fxed interference frequency. total jitter (tj) is the combination of random jitter and deterministic jitter: , where is a factor based on total test sample count. jedec std. specifes digital clock tj in 10k random samples. phase jitter phase noise is short-term random noise attached on the clock carrier and it is a function of the clock ofset from the car - rier, for example dbc/hz@10khz which is phase noise power in 1-hz normalized bandwidth vs. the carrier power @10khz ofset. integration of phase noise in plot over a given frequency band yields rms phase jitter, for example, to specify phase jitter <=1ps at 12k to 20mhz ofset band as sonet standard specif - cation. device thermal calculation fig. 13 shows the jedec thermal model in a 4-layer pcb. fig. 13 jedec ic termal model important factors to infuence device operating temperature are: 1) te power dissipation from the chip (p_chip) is afer subtract - ing power dissipation from external loads. generally it can be the no-load device idd 2) package type and pcb stack-up structure, for example, 1oz 4 layer board. pcb with more layers and are thicker has better heat dissipation 3) chassis air fow and cooling mechanism. more air fow m/s and adding heat sink on device can reduce device fnal die junc - tion temperature tj te individual device thermal calculation formula: tj =ta + pchip x ja tc = tj - pchip x jc ja ___ package thermal resistance from die to the ambient air in c/w unit; tis data is provided in jedec model simulation. an air fow of 1m/s will reduce ja (still air) by 20~30% jc ___ package thermal resistance from die to the package case in c/w unit tj ___ die junction temperature in c (industry limit <125c max.) ta ___ ambiant air temprature in c tc ___ package case temperature in c pchip___ ic actually consumes power through iee/gnd cur - rent PI6C5922504 rev a 08/14/2014 PI6C5922504 2.5 ghz 1:4 lvds fanout bufer with internal termination 14-0127
11 termal calculation example to calculate tj and tc of pi6cv304 in an soic-8 package: step 1: go to pericom web to fnd ja=157 c/w, jc=42 c/w http://www.pericom.com/support/packaging/packaging-me - chanicals-and-thermal-characteristics/ step 2: go to device datasheet to fnd idd=40ma max. step 3: p_total= 3.3vx40ma=0.132w step 4: if ta=85c tj= 85 + ja xp_total= 85+25.9 = 105.7c tc= tj + jc xp_total= 105.7- 5.54 = 100.1c note: te above calculation is directly using idd current without sub - tracting the load power, so it is a conservative estimation. for more precise thermal calculation, use p_unload or p_chip from device iee or gnd current to calculate tj, especially for lvpecl bufer ics that have a 150ohm pull-down and equivalent 100ohm diferential rx load. PI6C5922504 rev a 08/14/2014 PI6C5922504 2.5 ghz 1:4 lvds fanout bufer with internal termination 14-0127
12 pericom semiconductor corporation ? 1-800-435-2336 ? www .pericom.com ordering information (1,2,3) ordering code package code package description PI6C5922504zhie zh pb-free & green, 16-pin qfn notes: 1. t hermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. e = pb -free & green 3. x s uffx = tape/reel packaging mechanical: 16-pin tqfn (zh) PI6C5922504 rev a 08/14/2014 PI6C5922504 2.5 ghz 1:4 lvds fanout bufer with internal termination 14-0127

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